HP BIOS Post Procedures:
| CPU | Registers in CPU tested with data patterns, error flags are set, verified and reset |
| ROM BIOS Checksum | Checksums are performed on high and low BIOS chips |
| PIC Test | Test timer channels 0-2 then the memory refresh signal. Initialize timer if tests are passed. Check the 8254 chip |
| 64K Test | Walking bit and address collision tests are performed on the first 64K of memory. Check for a bad memory chip or address line |
| Cache Controller | The the CPU cache controller and memory |
| Video Adapter | Initialize the video adapter. If EGA.VGA is present, wait for the adapter to finish internal diagnostics. Check for adapter or improper setup if a failure occurs |
| DMA Test | Bit patterns written to all DMA controller registers, including page registers, and verifies the patterns written. If the tests pass the registers are reset and the controller initialized |
| PIC Test | Test mask register of master and slave interrupt controllers. Generate interrupt and monitor CPU to test success. Failure is normally down to the PIC but the interrupt test uses the BIOS clock (interrupt) and the RTC, so check those also |
| Keyboard Controller | Perform several tests on the 8042 keyboard controller then send a series of interrupt request commands via the 8259 PIC |
| HP-HIL Test | Test the HP-HIL (Hardware Interrupt Level) controller with data patterns and verify it |
| CMOS Test | Perform a checksum on the standard and extended CMOS RAM area. Perform a register test and check byte 0D to determine power status. Check the CMOS extended CMOS RAM or battery respectively if a failure occurs |
| Manufacturing Loop | Search for diagnostic tool used in manufacturing and run predetermined tests if found. Otherwise continue POST |
| Base Memory Test | Test RAM between 64K and 640K with several pattern test. The bit failure and bank can be determined by the displayed hex code |
| Extended Memory Test | Test extended memory found. Bank and failing bit displayed by the hex code |
| RTC Test | Test the RTC portion of the CMOS chip |
| Keyboard Controller | Test keyboard controller. Initialize keyboard if no errors found |
| Floppy Disk | Test and initialize floppy controllers and drives found. Check specific errors with the displayed hex code. Check for correct setup or defective CMOS chip or defective battery |
| Math Coprocessor | Test NPU registers and interrupt request functions |
| CPU Clock Test | Test interface between CPU and system at different speeds. Check for incorrect clock setting for system peripherals or a bad CPU or clock generator chip |
| Serial and Parallel Test | Test and initialize serial and parallel ports. Failure here will not halt the POST. The Vectra RS BIOS does not test the parallel port |
| Boot | Initialize the BIOS vector table, standard and extended CMOS data areas and any adapter ROM’s present. Then call Int 19 boot loader and give control to it. Failures past this point usually point to the hard drive or corrupt bootloader code |
HP Vectra BIOS Post Codes:
| 01 | LED test |
| 02 | Processor test |
| 03 | System (BIOS) ROM test |
| 04 | RAM refresh timer test |
| 05 | Interrupt RAM test |
| 06 | Shadow the system ROM BIOS |
| 07 | CMOS RAM test |
| 08 | Internal cache memory test |
| 09 | Initialize the video card |
| 10 | Test external cache |
| 11 | Shadow option ROM’s |
| 12 | Memory subsystem test |
| 13 | Initialize EISA/ISA hardware |
| 14 | 8042 keyboard controller self test |
| 15 | Timer 0 / Timer 2 test |
| 16 | DMA subsystem test |
| 17 | Interrupt controller test |
| 18 | RAM address line independence test |
| 19 | Size extended memory |
| 20 | Real mode memory test (first 640K) |
| 21 | Shadow RAM test |
| 22 | Protected mode RAM test (extended RAM) |
| 23 | Real time clock test |
| 24 | Keyboard test |
| 25 | Mouse test |
| 26 | Hard disk test |
| 27 | LAN test |
| 28 | Flexible disk controller subsystem test |
| 29 | Internal numeric coprocessor test |
| 30 | Weitek coprocessor test |
| 31 | Clock speed switching test |
| 32 | Serial port test |
| 33 | Parallel port test |
HP Vectra ES BIOS Post Codes:
| 000F | 80286 CPU is bad |
| 0010 | Bad checksum on ROM 0 |
| 0011 | Bad checksum on ROM 1 |
| 011X | One of the RTC registers is bad; Register = x(0-D) |
| 0120 | RTC failed to tick |
| 0240 | CMOS/RTC has lost power |
| 0241 | Invalid checksum, IBM CMOS area |
| 0280 | Invalid checksum, HP CMOS area |
| 02XY | One of the CMOS registers is bad; Register = XY – 40 |
| 0301 | 8042 failed to accept the reset command |
| 0302 | 8042 failed to respond to the reset command |
| 0303 | 8042 failed to reset |
| 0311 | 8042 failed to accept the “WRITE CMD BYTE” command |
| 0312 | 8042 failed to accept the data of the above command |
| 0321 | 8042 failed to accept scancode from port 68 |
| 0322 | 8042 failed to respond to the above scancode |
| 0323 | 8042 responded incorrectly to the above scancode |
| 0331 | 8042 failed to accept command from port 6A |
| 0332 | 8042 failed to generate SVC on port 67 |
| 0333 | 8042 generated HPINT type on port 65 |
| 0334 | 8042 failed the R/W register on port 69 |
| 0335 | 8042 failed to generate HPINT on IRQ 15 |
| 0336 | 8042 failed to generate HPINT on IRQ 12 |
| 0337 | 8042 failed to generate HPINT on IRQ 11 |
| 0338 | 8042 failed to generate HPINT on IRQ 10 |
| 0339 | 8042 failed to generate HPINT on IRQ 7 |
| 033A | 8042 failed to generate HPINT on IRQ 5 |
| 033B | 8042 failed to generate HPINT on IRQ 4 |
| 033C | 8042 failed to generate HPINT on IRQ 3 |
| 0341 | 8042 failed keyboard interface test command |
| 0342 | 8042didn’t respond to interface command |
| 0343 | Keyboard clock line stuck low |
| 0344 | Keyboard clock line stuck high |
| 0345 | Keyboard data line stuck low |
| 0346 | Keyboard data line stuck high |
| 0350 | No ACK from keyboard self test command |
| 0351 | Bad ACK from keyboard self test command |
| 0352 | Keyboard is dead or not connected |
| 0353 | No result from keyboard self test command |
| 0354 | Keyboard self test failed |
| 0401 | 8042 failed to enable gate A-20 |
| 0503 | Serial port dead or non existent |
| 0505 | Serial port fails port register tests |
| 0543 | Parallel port dead or non-existent |
| 06XX | Stuck key; XX=scancode of key |
| 0700 | Failed to switch to slow mode |
| 0701 | Failed to switch to dynamic mode |
| 0702 | Timer (channel 0) failed to interrupt |
| 0703 | Memory cycles too slow in slow mode |
| 0704 | Memory cycles too fast in slow mode |
| 0705 | I/O cycles too slow in slow mode |
| 0706 | I/O cycles too fast in slow mode |
| 0707 | Memory cycles too slow in dynamic mode |
| 0708 | Memory cycles too fast in dynamic mode |
| 0709 | I/O cycles too slow in dynamic mode |
| 070A | I/O cycles too fast in dynamic mode |
| 110X | One of the timer channels failed to register test / X(0-2)=channel that failed |
| 1200 | Memory refresh signal stuck high |
| 1201 | Memory refresh signal stuck low |
| 211X | DMA 1 failed R/W test at register x (0-7) |
| 212X | DMA 2 failed R/W test at register x (0-7) |
| 221X | Bad DMA page register; X=register 0-7 |
| 300X | HP-HIL controller failed self test; X=data |
| X = xx1 = >read/write fail with data = 0DA5h | |
| X = xx1x = >read/write fail with data = 0DA5h | |
| X = x1xx = >read/write fail with data = 0DA5h | |
| X = 1xxx = >read/write fail with data = 0DA5h | |
| 3010 | HP-HIL device test failed |
| 4XYZ | Lower 640K failed R/W test; |
| X=0,2,4,6 Y>0=Bad U23 Z>0=Bad U13 | |
| X=1,3,5,7 Y>0=Bad U43 Z>0=Bad U33 | |
| X=8 Y>0=Bad U22 Z>0=Bad U12 | |
| X=9 Y>0=Bad U42 Z>0=Bad U32 | |
| 5XYZ | Lower 640K failed marching ones test |
| X = bbbx = > bbb (0-7) is # of 128K bank | |
| bbb0 = > Indicate even byte bad | |
| bbb1 = > Indicate odd byte bad | |
| YZ = bbbb bbbb = > Bits for which b = 1 are bad | |
| 61XY | RAM address line XY stuck |
| Some address lines to RAM are stuck to 0 or 1 | |
| XY = 00bb bbbb = > RAM address line bbbbbb is stuck | |
| XY = 01bb bbbb = > Multiple address lines are stuck (bbbbbb is the first bad one) | |
| 620X | Lower 640K parity error; Bank X |
| X = Address in 64K bank where parity error occurred | |
| if X = 0 to y, U21 and/or U31 is/are bad | |
| if X = 8 to 9, U11 and/ore U41 is/are bad | |
| 63XY | Parity error above 1MB; Bank XY |
| Parity error has occurred during RAM test above the first MB | |
| XY = Address in 64K bank where parity occurred | |
| 6400 | Parity generator failed to detect error |
| 71XY | Master 8259 failed R/W; bits XY |
| XY = bbbb bbbb + > bits in which b = 1 is bad | |
| 72XY | Slave 8259 failed R/W; bits XY |
| XY = bbbb bbbb = > bits in which b = 1 is bad | |
| 7400 | Master 8259 failed interrupt |
| 7500 | Slave 8259 failed interrupt |
| 9XYZ | Floppy drive controller error |
| X=drive # | |
| Y=0=1st level error | |
| Z=0 Unsuccessful input from FD | |
| Z=1 Unsuccessful output to FDC | |
| Z=2 Error while executing seek | |
| Z=3 Error during recalibrate | |
| Z=4 Error verifying RAM buffer | |
| Z=5 Error while resetting FDC | |
| Z=6 Wrong drive identified | |
| Z=7 Wrong media identified | |
| Z=8 No interrupt from FDC | |
| Z=9 Failed to detect track 0 | |
| Z=A Failed to detect index pulse | |
| Y>1=Higher level error | |
| Y=1=Read sector error, side 0 | |
| Y=2=Read sector error, side 1 | |
| Y=3=Write sector error, side 0 | |
| Y=4=Write sector error, side 1 | |
| Y=5=Format sector error, side 0 | |
| Y=6=Format sector error, side 1 | |
| Y=7=Read ID error, side 0 | |
| Y=8=Read ID error, side 1 | |
| Z=1=No ID address mark | |
| Z=2=No data address mark | |
| Z=3=Media is write protected | |
| Z=4=Sector # wrong | |
| Z=5=Cylinder # wrong | |
| Z=6=Bad cylinder | |
| Z=7=DMA overrun | |
| Z=8=ID CRC error | |
| Z=9=Data CRC error | |
| Z=A=End of cylinder | |
| Z=B=Unrecognizable error | |
| A001 | No 80287 detected |
| A002 | 80287 failed stack register R/W test |
| A00C | No zero-divide interrupt from 80287 |
| CXYZ | R/W error on extended RAM in XY bank |
| Read/Write test failure on extended RAM | |
| X = 0 = > Even byte is bad | |
| X = 1 = > Odd byte is bad | |
| XY = Address in 64K bank where RAM failed | |
| CFFF | Extended RAM marching ones failed |
| Marching on test failure on extended RAM | |
| X = 0 = > Even byte bad | |
| X = 1 = > Odd byte bad | |
| XA = Address in 64K bank where RAM failed |
HP Vectra QS & RS BIOS Post Codes:
| 000F | 386 CPU bad |
| 0010 | Bad checksum on ROM 0 |
| 0011 | Bad checksum on ROM 1 |
| 011X | RTC register is bad |
| 0120 | RTC failed to tick |
| 0240 | CMOS/RTC lost power |
| 0241 | Invalid checksum, IBM CMOS area |
| 0280 | Invalid checksum, HP CMOS area |
| 02XY | Bad CMOS register, at XY-40 |
| 0301 | 8042 failed to accept reset command |
| 0302 | 8042 failed to respond to reset |
| 0303 | 8042 failed on reset |
| 0311 | 8042 didn’t accept “WRITE CMD BYTE” |
| 0312 | 8042 didn’t accept data |
| 0321 | 8042 failed to accept scancode, port 68 |
| 0322 | 8042 failed to respond to the above scancode |
| 0323 | 8042 responded incorrectly to the above scancode |
| 0331 | 8042 failed to accept command from port 6A |
| 0332 | 8042 failed to generate SVC on port 67 |
| 0333 | 8042 generated HPINT type on port 65 |
| 0334 | 8042 failed the R/W register on port 69 |
| 0335 | 8042 failed to generate HPINT on IRQ 15 |
| 0336 | 8042 failed to generate HPINT on IRQ 12 |
| 0337 | 8042 failed to generate HPINT on IRQ 11 |
| 0338 | 8042 failed to generate HPINT on IRQ 10 |
| 0339 | 8042 failed to generate HPINT on IRQ 7 |
| 033A | 8042 failed to generate HPINT on IRQ 5 |
| 033B | 8042 failed to generate HPINT on IRQ 4 |
| 033C | 8042 failed to generate HPINT on IRQ 3 |
| 0341 | 8042 failed keyboard interface test command |
| 0342 | 8042didn’t respond to interface command |
| 0343 | Keyboard clock line stuck low |
| 0344 | Keyboard clock line stuck high |
| 0345 | Keyboard data line stuck low |
| 0346 | Keyboard data line stuck high |
| 0350 | No ACK from keyboard self test command |
| 0351 | Bad ACK from keyboard self test command |
| 0352 | Keyboard is dead or not connected |
| 0353 | No result from keyboard self test command |
| 0354 | Keyboard self test failed |
| 0401 | 8042 failed to enable gate A-20 |
| 0503 | Serial port dead or non-existent |
| 0505 | Serial port fails port register tests |
| 06XX | Stuck key; XX=scancode of key |
| 0700 | Failed to switch to slow speed |
| 0701 | Failed to switch to fast speed |
| 0702 | Timer failed to interrupt |
| 0703 | CPU clock too slow in slow speed |
| 0704 | CPU clock too fast in slow speed |
| 0707 | CPU clock too slow in fast speed |
| 0708 | CPU clock too fast in fast speed |
| 0709 | Failed to switch bus clock to ATCLK |
| 110X | Timer X (0-2) failed to register test |
| 1200 | Memory refresh signal stuck high |
| 1201 | Memory refresh signal stuck low |
| 211X | DMA 1 failed R/W test at register x (0-7) |
| 212X | DMA 2 failed R/W test at register x (0-7) |
| 221X | Bad DMA page register; X=register 0-7 |
| 300X | HP-HIL controller failed self test; X=data |
| X = xxx1 = > read/write fail with data = 0DA5Ah | |
| X = xx1x = > read/write fail with data = 0DA5Ah | |
| X = x1xx = > read/write fail with data = 0DA5Ah | |
| X = 1xxx = > read/write fail with data = 0DA5Ah | |
| 3010 | HP-HIL device test failed |
| 4XYZ | Lower 640K failed R/W test; |
| X=0,2,4,6 Y>0=Bad U23 Z>0=Bad U13 | |
| X=1,3,5,7 Y>0=Bad U43 Z>0=Bad U33 | |
| X=8 Y>0=Bad U22 Z>0=Bad U12 | |
| X=9 Y>0=Bad U42 Z>0=Bad U32 | |
| 5XYZ | Lower 640K failed marching ones test |
| RAM in lower 640K failed read/write test | |
| X = bbcc = > bb is # 64K of 32 bit word bank | |
| cc = 00 = > byte 0 is bad | |
| cc = 01 = > byte 1 is bad | |
| cc = 02 = > byte 2 is bad | |
| cc = 03 = > byte 3 is bad | |
| YZ = bbbb bbbb = > bits for which b = 1 are bad | |
| 61XY | RAM address line XY stuck |
| Some address lines to RAM are stuck to 0 or 1 | |
| XY = 00bb bbbb = > RAM address line bbbbbb is stuck | |
| XY = 01bb bbbb = > Multiple address lines are stuck bbbbbb is the first bad one | |
| 620X | Lower 640K parity error; Bank X |
| X = Address in 64K bank where parity occurred | |
| 63XY | Parity error above 1MB; Bank XY |
| XY = Address in 64K bank where parity occurred | |
| 6500 | Shadow RAM bad at BIOS segment |
| 6510 | Shadow RAM bad at HP EGA segment |
| 71XY | Master 8259 failed R/W; bits XY |
| XY = bbbb bbbb = > bits which b = 1 is bad | |
| 72XY | Slave 8259 failed R/W; bits XY |
| XY = bbbb bbbb = > bits which b = 1 is bad | |
| 7400 | Master 8259 failed interrupt |
| 7500 | Slave 8259 failed interrupt |
| 9XYZ | Floppy drive controller error |
| X=drive # | |
| Y=0=1st level error | |
| Z=0 Unsuccessful input from FD | |
| Z=1 Unsuccessful output to FDC | |
| Z=2 Error while executing seek | |
| Z=3 Error during recalibrate | |
| Z=4 Error verifying RAM buffer | |
| Z=5 Error while resetting FDC | |
| Z=6 Wrong drive identified | |
| Z=7 Wrong media identified | |
| Z=8 No interrupt from FDC | |
| Z=9 Failed to detect track 0 | |
| Z=A Failed to detect index pulse | |
| Y>1=Higher level error | |
| Y=1=Read sector error, side 0 | |
| Y=2=Read sector error, side 1 | |
| Y=3=Write sector error, side 0 | |
| Y=4=Write sector error, side 1 | |
| Y=5=Format sector error, side 0 | |
| Y=6=Format sector error, side 1 | |
| Y=7=Read ID error, side 0 | |
| Y=8=Read ID error, side 1 | |
| Z=1=No ID address mark | |
| Z=2=No data address mark | |
| Z=3=Media is write protected | |
| Z=4=Sector # wrong | |
| Z=5=Cylinder # wrong | |
| Z=6=Bad cylinder | |
| Z=7=DMA overrun | |
| Z=8=ID CRC error | |
| Z=9=Data CRC error | |
| Z=A=End of cylinder | |
| Z=B=Unrecognizable error | |
| A001 | No 80287 detected |
| A002 | 80287 failed stack register R/W test |
| A00C | No zero-divide interrupt from 80287 |
| AF00 | Weitek coprocessor didn’t enter protected mode |
| AF01 | Weitek coprocessor nor present |
| AF02 | Weitek coprocessor fails register test |
| AF05 | Weitek coprocessor fails addition test |
| AF06 | Weitek coprocessor fails interrupt test |
| AF0C | Weitek coprocessor fails interrupt test |
| CXYZ | R/W error on extended RAM in XY bank |
| X = 0 = > Even byte bad | |
| X = 1 = > Odd byte bad | |
| XY = Address in 64K bank where RAM failed | |
| CFFF | No extended RAM found |
| EXYZ | Extended RAM marching ones failure at XYZ |
| X = 0 = > Byte 0 is bad | |
| X = 1 = > Byte 1 is bad | |
| X = 2 = > Byte 2 is bad | |
| X = 3 = > Byte 3 is bad |
HP Pavilion Series 3100 & 8000 BIOS Post Codes:
| 02 | Verify real mode |
| 03 | Disable NMI |
| 04 | Get processor type |
| 06 | Initialize system hardware |
| 08 | Initialize chipset with POST values |
| 09 | Set IN-POST flags |
| 0A | Initialize CPU registers |
| 0B | Enable CPU registers |
| 0C | Initialize cache to POST values |
| 0E | Initialize I/O component |
| 0F | Initialize local IDE bus |
| 10 | Initialize power management |
| 11 | Load alternate registers |
| 12 | Restore CPU control word during warm boot |
| 13 | Initialize PCI bus mastering devices |
| 14 | Initialize keyboard controller |
| 16 | BIOS ROM checksum |
| 17 | Initialize cache before memory size |
| 18 | Initialize 8254 timer |
| 1A | Initialize DMA controller |
| 1C | Reset PIC |
| 20 | Test DRAM refresh |
| 22 | Test 8742 keyboard controller |
| 24 | Set ES segment register to 4GB |
| 26 | Enable A-20 line |
| 28 | Autosize DRAM |
| 29 | Initialize POST memory manager |
| 2A | Clear 512K base RAM |
| 2C | RAM address line failure |
| 2E | RAM data failure, low byte |
| 2F | Enable cache before BIOS shadow |
| 30 | RAM data failure, high byte |
| 32 | Test CPU, BUS clock frequency |
| 33 | Initialize POST dispatch manager |
| 34 | Test CMOS RAM |
| 35 | Initialize alternate chipset registers |
| 36 | Warm start shut-down |
| 37 | Reinitialize chipset (MB only) |
| 38 | Shadow system BIOS ROM |
| 39 | Reinitialize cache (MB only) |
| 3A | Autosize cache |
| 3C | Configure advanced chipset registers |
| 3D | Load alternate registers new CMOS values |
| 40 | Set initial CPU speed |
| 42 | Initialize interrupts |
| 44 | Initialize BIOS interrupts |
| 45 | POST device initialization |
| 46 | Check ROM copyright notice |
| 47 | Initialize manager for PCI option ROM’s |
| 48 | Check video config against CMOS |
| 49 | Initialize manager for PCI option ROM’s |
| 4A | Initialize all video adapters |
| 4B | Display quiet boot screen |
| 4C | Shadow video BIOS |
| 4E | Display BIOS copyright notice |
| 50 | Display CPU type & speed |
| 51 | Initialize |
| 52 | Test keyboard |
| 54 | Set key click if enabled |
| 56 | Enable keyboard |
| 58 | Test for unexpected interrupts |
| 59 | Initialize POST display service |
| 5A | Display “Press F2 to Enter Setup” |
| 5B | Disable CPU cache |
| 5C | Test RAM, 512-640K |
| 60 | Test extended memory |
| 62 | Test extended memory address lines |
| 64 | Jump to user patch 1 |
| 66 | Configure advanced cache registers |
| 67 | Initialize multi-processor APIC |
| 68 | Enable external & processor caches |
| 69 | Set up SMM area |
| 6A | Display external L2 cache size |
| 6C | Display shadow area message |
| 6E | Display high address for UMB recovery |
| 70 | Display error message |
| 72 | Check for configuration errors |
| 74 | Test real time clock |
| 76 | Check for keyboard errors |
| 7A | Test for key lock on |
| 7C | Set up hardware interrupt vectors |
| 7E | Initialize coprocessor, if present |
| 80 | Disable onboard super I/O ports |
| 81 | Late POST device initialization |
| 82 | Detect & install external RS-232 ports |
| 83 | Configure non-MDC IDE controllers |
| 84 | Detect & install external parallel ports |
| 85 | Initialize PnP ISA devices |
| 86 | Reinitialize onboard I/O ports |
| 87 | Configure motherboard configurable devices |
| 88 | Initialize BIOS data area |
| 89 | Enable NMI’s |
| 8A | Initialize extended BIOS data area |
| 8B | Test & initialize PS/2 mouse |
| 8C | Initialize floppy controller |
| 8F | Determine number of ATA drives |
| 90 | Initialize hard disk controllers |
| 91 | Initialize local BUS HD controllers |
| 92 | Jump to user patch 2 |
| 93 | Build MPTABLE for multiprocessor boards |
| 94 | Disable A-20 line |
| 95 | Install CD-ROM for boot |
| 96 | Clear huge ES segment register |
| 97 | Fix up multiprocessor table |
| 98 | Search for options ROM’s |
| 99 | Check for smart drive |
| 9A | Shadow ROM option |
| 9C | Set up power management |
| 9E | Enable hardware interrupts |
| 9F | Determine number of ATA & SCSI drives |
| A0 | Set time of day |
| A2 | Check key lock |
| A4 | Initialize typematic rate |
| A8 | Erase F2 prompt |
| AA | Scan for F2 keystroke |
| AC | Enter SETUP |
| AE | Clear IN-POST flag |
| B0 | Check for errors |
| B2 | POST done, prepare for boot |
| B4 | One short beep before boot |
| B5 | Terminate quiet boot |
| B6 | Check password (optional) |
| B8 | Clear global descriptor table |
| B9 | Clean up all graphics |
| BA | Initialize DMI parameters |
| BB | Initialize PnP option ROM’s |
| BC | Clear parity checkers |
| BD | Display multi boot menu |
| BE | Clear screen optional |
| BF | Check virus and backup reminders |
| C0 | Try to boot with Int 19 |
| C1 | Initialize POST error manager |
| C2 | Initialize error logging |
| C3 | Initialize error display function |
| C4 | Initialize system error handler |
| E0 | Initialize the chipset |
| E1 | Initialize the bridge |
| E2 | Initialize the processor |
| E3 | Initialize system timer |
| E4 | Initialize system I/O |
| E5 | Check force recovery boot |
| E6 | Checksum BIOS ROM |
| E7 | Got to BIOS |
| E8 | Set huge segment |
| E9 | Initialize multiprocessor |
| EA | Initialize OEM special code |
| EB | Initialize PIC & DMA |
| EC | Initialize memory type |
| ED | Initialize memory type |
| EE | Shadow boot block |
| EF | System memory test |
| F0 | Initialize interrupt vectors |
| F1 | Initialize runtime clock |
| F2 | Initialize video |
| F3 | Initialize beeper |
| F4 | Initialize BOOT |
| F5 | Clear huge segment |
| F6 | Boot to mini-DOS |
| F7 | Boot to full DOS |